Electronic Design Automation (EDA) is used to design and simulate electronic circuits. A functional chip architecture is developed and implemented in register transfer level (RTL) language by a system designer. The RTL is assigned to regions of a chip (e.g., by assignment of I/O pins), and the RTL is mapped into a combinational logic gate level netlist, e.g., a Verilog netlist. A netlist describes the connectivity of components of the circuit. More particularly, a netlist provides instances of components and nets. Instances are realized from a component library, e.g. a resistor, capacitor, and other circuit components. Nets are wires that connect the circuit components together. The circuit design typically includes spare cells, which are provided in the event that changes must be made to the circuit design at a later time. In an exemplary circuit design may have about 90-95% of the gates form the circuit design and about 5-10% of the gates are spare cells.
A technology mapper receives the net list, determines gates that are available from a component or gate library, and modifies and optimizes the netlist based on the components available from the library and design constraint considerations. Further details regarding exemplary technology mappers can be found in U.S. Pat. Nos. 6,378,116; 6,405,345 and 6,519,743, the contents of which are incorporated herein by reference.
A layout designer determines how to place and route the design that is provided by the system designer. Netlist gates are assigned to or placed on locations of the chip, and a router is used to connect gates in the netlist with wires. More particularly, a placer element takes a given netlist together with the parts library and determines the location of the components on a chip to produce a circuit layout, which can then be optimized to satisfy certain design constraints. A router generates wires that connect the placed components. The “placed and routed” design on silicon can then be verified to confirm that the circuit functions according to the design, and the final design is turned into a mask, which is used to fabricate the circuit.
The design process, however, can be complicated by Engineering Change Orders (ECOs) or modifications that require changes to the circuit design. The modification may be necessary to address a problem or provide additional functionality. Such modifications can be difficult to implement, particularly when design changes are made late in the design process. For example, a layout designer may have a placed and routed design that is partially manufactured so that front-end layers are already manufactured, but back-end layers (routing layers) are not yet manufactured. An ECO may require that some logical connectivity must be updated in the placed and routed netlist to fix a bug or to add additional functionality. An issue may also arise in the context of a placed and routed design that is completely manufactured, but there is a timing yield problem. Debugging may determine that the yield problem is caused by an instance being faster than expected and introducing a hold time violation, or an instance may be slower than expected and introduces setup time violations. These modifications can be difficult to address at these stages of the design process in view of the work and manufacturing that has already been completed. Often times, these changes must be made using spare cells.
Spare cells are free or available cells that can be used to implement design changes. However, there may only be a few spare cells, the location of the spare cells may not be satisfactory, and the placement options may be limited. For example, the spare cell may be located far away from another circuit component, thereby introducing timing delays, which can be particularly problematic if the change involves the critical or longest path in the circuit. These constraints can further complicate the manner in which design modifications are completed, particularly late in the process when the circuit or chip is partially or completely manufactured.
One known solution is to simply discard the partially or completely fabricated wafers, re-design the placed and routed netlist, generate new masks (front-end and back-end) and re-manufacture the circuit. This solution is not desirable given the substantial costs and time associated with substantial re-designs and discarded wafers. Another known solution is to have a designer alter manually placed and routed design. However, manual reworks can be very labor intensive, expensive, and prone to errors. Further, manual reworks can become very complicated with increasing numbers of gates and can require days, weeks or months to complete.
Further, assuming the ECO is implemented, the resulting design may not satisfy design constraints. For example, available spare cells may be located far away from the critical path so that timing issues are not resolved. Current systems do not adequately address these issues.
Accordingly, there exists a need in the art for a method that can automatically update a placed and routed design to overcome the shortcomings associated with known techniques. The method should effectively manage and allocate spare cells as needed and allow for automatically updates 20 circuit designs without the need to discard partially or completely manufactured circuit components. The method should also reduce or minimize the amount of manual work that is required to implement design changes. The method should be flexible and should respect design constraints, such as timing and yield. Embodiments of the invention fulfill these unmet needs.